The present invention relates to an output circuit of a semiconductor device, and more particularly, to an output circuit of a semiconductor device which is capable of reducing jitter caused by limiting a swing width/a voltage swing of an output signal. The swing width of the output signal signifies a voltage width between a high voltage level and a low voltage level thereof.
FIG. 1 is a block diagram showing a conventional output circuit for a semiconductor device.
As shown, the conventional output circuit includes a first pass gate, 101, a second pass gate 103, and an output inverter 105. If a first clock signal is inputted to the first pass gate 101 and the second pass gate 103, the first pass gate 101 is turned on so that a first input signal DATA 1 is outputted through the output inverter 105. The phase of a second clock signal is opposed to that of the first clock signal.
If the second clock signal is inputted to the first pass gate 101 and the second pass gate 103, the second pass gate 103 is turned on so that a second input signal DATA 2 is outputted through the output inverter 105.
FIG. 2 is another block diagram illustrating a conventional output circuit used in a semiconductor device.
As shown in FIG. 2, a first tri-state inverter 201 and a second tri-state inverter 203 are used instead of the first pass gate 101 and the second pass gate 103. The first and second tri-state inverters 201 and 203 inherently include an inverter functioning differently from a pass gate. Therefore, the output circuit does not use the inverter in front of the first tri-state inverter 201 and the second tri-state inverter 203 in order to obtain the same output with the output circuit shown in FIG. 1. Except for this point, the output circuit has the same configuration as the output circuit shown in FIG. 1.
The output circuit may output signals in series wherein input signals are inputted in parallel. In this case, the output circuit employs the first and second clock signals as control signals, wherein each of the clock signals has a phase opposite to the other, and is inputted to the output circuit.
In a conventional output circuit, two pass gates 101 and 103 or two inverters 201 and 203 are connected to the output inverter 105 at a node A where a high capacitance exists. The high capacitance is caused by a gate capacitance of the output inverter 105 and a junction capacitance of two pass gates 101 and 103 or two inverters 210 and 203.
High capacitance appearing on node A limits the swing width of a out signal having high frequency. Here, the swing width means voltage width/span between a high voltage level and a low voltage level of the output signal. An output signal having low frequency is not influenced by high capacitance. On the other hand, an output signal having high frequency is restricted in the swing width due to high capacitance. Consequently, the swing width of the output signal having the high frequency is limited.
Here, frequency means the number of transitions of voltage levels of an output signal per unit time. Therefore, an output signal having the low frequency means that the output signal has a small number of transitions.
For example, when both of the first and second input signals inputted in parallel to the output circuit shown in FIGS. 1 and 2, have a high voltage level or a low voltage level, the output circuit consecutively outputs high or low voltage levels. In this case, an output signal having a small number of transitions of logic voltage level is regarded as a low frequency output signal.
On the other hand, when the first and second input signals inputted in parallel to the output circuit shown in FIGS. 1 and 2, and one input signal has a high voltage level while the other has a low voltage level, an output signal of the output circuit of FIGS. 1 and 2 transits from high voltage to low voltage level. That is, if the output signal has a large number of transitions of a logic level, then it is regarded as a high frequency output signal.
Consequently, the swing width of an output signal having a high frequency is limited due to the high capacitance, and this cause a problem of jitter appearing in the output signal. Specifically, this problem may become serious if the output circuit operates at high speed.